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Cellular ASIC Design Engineer

Apple· Hardware
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San Diego, CA, Austin, TX, Sunnyvale, CA$175k - $308.5kFull-timePosted 7mo ago

About the role

Role within Apple’s Hardware Technologies group focusing on designing, optimizing, and manufacturing next-generation cellular chips and SoCs with emphasis on area efficiency, power optimization, and design technology co-optimization across advanced process nodes.

Responsibilities

  • Establish design guidelines, methodologies, and standards for synthesis, place-and-route, timing closure, and signoff processes
  • Develop and optimize EDA tool flows including synthesis, P&R, and signoff tools
  • Drive timing convergence process improvements across design teams to enhance PPA and yield
  • Create and maintain design flows, scripts, and automation tools to improve design productivity
  • Identify utilization bottlenecks in physical design and develop solutions to improve utilizations
  • Work with physical design teams on timing closure and validate flows/tools with CAD/IP/DT teams
  • Understand RTL to GDS digital flow and contribute to timing signoff of complex SOCs
  • Perform design technology co-optimization analysis and optimal operating point analysis for performance/power
  • Conduct Spice simulations for PVT corners validation and STA vs spice correlation
  • Perform timing package validation and develop timing signoff specifications
  • Analyze design databases and silicon validation data to identify issues and improve metrics
  • Understand intricate timing paths and provide timing constraint solutions as required
  • Develop and implement voltage scaling and power optimization methodologies including clock gating and DVFS
  • Use power analysis tools for power signoff and optimization
  • Improve STA methodologies and ECO processes
  • Collaborate with technology/IP teams to enhance efficiency via IP development
  • Support advanced process technology bring-up from PDK to production
  • Drive DFT methodology improvements including scan insertion and ATPG
  • Stay ahead of industry trends and apply programming (Python, Perl, TCL, Unix shell, C/C++) for automation
  • Apply ML modeling for advanced design optimization and predictive analysis

Qualifications

  • Minimum BS and 10+ years of relevant industry experience
  • VLSI background with hands-on RTL to GDSII flows
  • Experience with Power, Performance, Area and Cost optimizations for SoCs
  • Experience with SoC power flows & Vmin optimization
  • Experience with Design Technology Co-optimization and solving scaling bottlenecks in new tech nodes
  • Rapid prototyping and scripting of methodologies and test chip block implementation
  • Solid understanding of Physical Design challenges, synthesis, place-and-route tools, and implementation exploration
  • Experience with Metal stack optimizations
  • Experience performing Early Tech node analysis to identify bottlenecks
  • Design Technology Co-optimization expertise
  • Strong analytical skills and ROI-oriented mindset
  • Ability to apply data science and ML analytics to frontend/backend and post-silicon data to refine methodologies

Skills

Required:PythonPerlTCLUnix shell
Nice to have:C/C++

Benefits

  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Discounted products and free services
  • Educational expense reimbursement including tuition
  • Discretionary bonuses or commissions (eligibility varies)
  • Relocation assistance (where applicable)
  • Apple shareholder opportunities through stock programs
  • Employee Stock Purchase Plan (ESPP)
Last updated Jul 24, 2026. Interested? Apply on the company site.

About Apple

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

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