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STA Engineer (M, F, D)

Apple· Hardware
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MunichFull-timePosted 7mo ago

About the role

Engineer role in the STA team engaged with integration teams to develop automated signoff flows, timing/noise convergence, and flow enhancements for full chip and block-level signoff, with emphasis on hierarchical timing, power optimization, and IP integration.

Responsibilities

  • Developing automated block and full chip level signoff flows
  • Full Chip Timing/Noise convergence and full signoff for high quality TO
  • Enabling hierarchical Timing flows
  • Power optimizations
  • Generating block level budget and context for correlation with Full Chip
  • Driving custom IP integration and custom timing checks flows
  • Closing work with Design, DFT, architecture and Power team

Qualifications

  • MSEE or equivalent strong experience in Static Timing analysis
  • Extensive experience with one of the commercial STA tools
  • Ability to fluently speak and write in English
  • Familiarity with hierarchical design approach, top-down design, timing and physical convergence
  • Experience with backend STA closure and Signoff
  • Deep understanding of designs' constraints development
  • Good understanding of AC timing from specs to implementation
  • Good understanding of DFT modes and their constraints
  • Good communication skills and team player
  • Quick learning of flows and methods
  • Advantage - Understanding noise and signal integrity effects
  • Advantage - Timing margins fundamental from synthesis to signoff
  • Advantage - Experience with scripting

Skills

Required:Static Timing Analysis (STA)STA tool proficiencyHierarchical timing & top-down designAC timingDFT constraintsCommunication & teamwork
Nice to have:Scripting

Benefits

  • Not specified in this description
Last updated Sep 18, 2026. Interested? Apply on the company site.

About Apple

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

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