Formal Verification Engineer
Apple· Hardware
Hybrid (Saint Albans, England)full-timePosted 7mo ago
About the role
Formal verification architect leading the complete formal verification for single or multiple design blocks and IPs, collaborating with design engineers to verify complex SoC architectures and ensure correct-by-construction design methodologies.
Responsibilities
- Lead the complete formal verification for one or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.).
- Develop a formal micro-architecture specification with design engineers.
- Formalize refinement from architecture to micro-architecture.
- Develop comprehensive formal verification test plans.
- Prove properties of the design, identify design bugs, and work with design teams to improve micro-architecture.
- Craft novel and creative solutions for verifying complex design micro-architectures.
- Develop and implement reusable and optimized formal models and verification code base.
- Architect correct-by-construction design methodologies for improved formal verification efficiency and productivity.
Qualifications
- BS / MS / Ph.D in EE or CS is required.
Skills
Required:VLSI and digital logic design and verification techniquesSoC/CPU/GPU or Cellular design knowledgeFormal property proofsPipeline architectures, memory/DMA controllers, out-of-order and speculative executionFormal verification technologies/abstraction techniquesHardware specification interpretationTemporal logic assertion languages (SVA or PSL)Scripting
Nice to have:EDA formal tools
Benefits
- Not specified in the description.
Last updated Jul 3, 2026. Interested? Apply on the company site.
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