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SoC Physical Design Engineer (M, F, D)

Apple· Hardware
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MunichFull-timePosted 6mo ago

About the role

SoC Digital Physical Design Engineer responsible for block-level PnR, floor-planning, clock and power distribution, timing closure, power/EM/IR-drop/XTalk analysis, and layout verification for a complex SoC using new process technology. Participates in end-to-end physical design flow from netlist to GDS, with emphasis on schedule and design goals, in a highly collaborative, multicultural Apple environment.

Responsibilities

  • Own block level PnR, floor-planning, clock and power distribution
  • Involve with static timing closure using commercial tools
  • Perform power and noise analysis (EM/IR-Drop/Xtalk) and layout verification (DRC/LVS)
  • Develop and validate dedicated low-power clock network guidelines
  • Resolve design/flow issues related to physical design and drive execution
  • Create and maintain design guidelines and specs
  • Implement design partitions (Netlist to final GDS) for a highly complex SoC using brand-new process technology
  • Collaborate within Physical Design team to ensure successful tape-outs and meeting schedules

Qualifications

  • MSEE or equivalent
  • Hands-on experience with one of the Place & Route (PnR) tools (Synopsys / Cadence)
  • Scripting/programming experience (Perl, TCL, Make)
  • Experience with large SoC designs (>20M gates) and frequencies >1 GHz
  • Verilog knowledge is a plus
  • Excellent communication and teamwork in open, multicultural environment
  • Familiarity with hierarchical/top-down design, timing/physical convergence
  • Strong understanding of static timing analysis, clock/power distribution, RC extraction and correlation
  • Experience with SoC practices including multiple voltage/clock domains, mixed-signal IP integration and I/O integration

Skills

Required:Block level PnRStatic timing analysisPower/EM/IR-Drop/XTalk analysisLayout verificationPnR tools (Synopsys / Cadence)Scripting (Perl, TCL, Make)Communication in multicultural environmentHierarchical/top-down design
Nice to have:Verilog
Last updated Oct 23, 2026. Interested? Apply on the company site.

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