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Design Verification Engineer

Apple· Hardware
Apply on company site
Beaverton, ORFull-timePosted 6mo ago

About the role

DV engineer role at Apple Beaverton focusing on pre-silicon verification for IP designs, developing scalable verification environments, test plans, and using LLMs to improve efficiency and quality.

Responsibilities

  • Study design specification and create test plan
  • Develop infrastructure in SystemVerilog/UVM to stress the design
  • Develop and fix failures from regressions, close bugs
  • Use LLMs to do verification efficiently

Qualifications

  • BS degree in technical subject area and a minimum 10 years relevant industry experience
  • Deep knowledge of OOP, SystemVerilog and UVM
  • Deep knowledge in developing scalable and portable test-benches
  • Strong experience with verification methodologies and tools such as simulators, waveform viewers, Build and run automation, coverage collection, gate level simulations
  • Working experience using LLMs for efficiency and quality
  • Experience with power-aware (UPF) or similar verification methodology
  • Excellent knowledge of one of the scripting languages such as Python, Perl, TCL
  • Experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
  • Knowledge of formal verification methodology is a plus but not required
  • Knowledge of emulation for verification technologies is a plus but not required

Skills

Required:SystemVerilogUVMOOPPython
Nice to have:Power-aware verification
Last updated Sep 11, 2026. Interested? Apply on the company site.

About Apple

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

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