Design Verification Engineer
About the role
In this visible role, you will be responsible for defining DV methodologies, test-bench infrastructure, and for project execution for the next generation Apple high-speed interfaces to enable groundbreaking I/O connectivity solutions for Apple product lines. You will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors, apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market, work closely with the design team, accelerate verification time, and participate in Post-Silicon Validation.
Responsibilities
- Define DV methodologies, test-bench infrastructure, and project execution for high-speed interface verification
- Develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors
- Apply advanced verification techniques to ensure quality, productivity, and time-to-market
- Collaborate with design and software teams to ensure timely delivery of quality designs
- Work on methods to accelerate verification time
- Involvement in Post-Silicon Validation
Qualifications
- 6+ years of experience in SoC Verification
- Advanced knowledge of SoC architecture/design and verification flows
- Deep understanding and experience in advanced verification processes (dynamic, coverage-based, formal methods)
- Extensive experience with System Verilog or UVM
- Experience with verification infrastructure development
- Scripting/Programming experience in Perl, Python, Verilog, SystemVerilog, C, C++, TCL (advantage)
- B.Sc or M.Sc in Electrical or Computer Engineering
Skills
About Apple
Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.
Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.
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