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SIPI Architect for High-Speed SerDes

Apple· Hardware
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Hybrid (Austin, TX), Hybrid (San Francisco Bay Area)Full-timePosted 6mo ago

About the role

Define and own the end-to-end signal and power integrity strategy for cutting-edge high-speed SerDes and guide system-level co-design across silicon, package, and system to ensure robust interconnect performance.

Responsibilities

  • Define and own the end-to-end SIPI (Signal and Power Integrity) architecture and strategy for cutting-edge high-speed SerDes links.
  • Drive the technical direction and build consensus across cross-functional teams, including circuit design, packaging, system hardware, and validation, to deliver robust interconnect solutions.
  • Lead system-level trade-off analysis to optimize interconnect performance, power, and cost across silicon, package, and system levels.
  • Influence Apple's technology roadmap by providing expert guidance on future interconnect technologies, advanced packaging, and system-level co-design.
  • Ensure robust interconnect design and performance by overseeing comprehensive modeling, simulation (statistical and time-domain), and silicon correlation.
  • Develop and champion next-generation SIPI methodologies and best practices to guide design and analysis.

Qualifications

  • BS and 20+ years of relevant industry experience.
  • MS or PhD in Electrical Engineering or a related field with 20+ years of relevant industry experience.
  • Deep expertise in system-level SIPI for high-speed SerDes (112G/224G and beyond).
  • Proven experience architecting solutions for high-performance interconnects using standards such as Ethernet, PCIe, UAL and CXL.
  • Expert in end-to-end channel modeling and link budget analysis, including statistical (e.g., COM) and time-domain simulation.
  • In depth understanding of SerDes TX/RX equalization techniques, clocking and power delivery trade-offs.
  • Experience leading cross-functional teams and driving technical consensus across silicon architecture, circuit design, packaging and system hardware groups.
  • Experience designing interconnects for large-scale systems such as those in data center or high-performance computing (HPC) environments.
  • Familiarity with emerging interconnect technologies, including co-packaged optics (CPO), and advanced packaging (e.g., 2.5D/3D integration).
  • Familiarity with system-level power integrity (PDN) and thermal co-design for large-scale, high-power ASICs.

Skills

Required:SIPI (Signal and Power Integrity) architectureHigh-speed SerDes (112G/224G and beyond)Interconnect standardsChannel modeling and link budgetSerDes techniques
Last updated Aug 21, 2026. Interested? Apply on the company site.

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