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CPU Cache Microarchitect/RTL Engineer

Apple· Hardware
Apply on company site
Santa Clara, California, Beaverton, Oregon, Waltham, Massachusetts$184.7k - $324.8kfull-timePosted 6mo ago

About the role

Apple Silicon Engineering Group seeks an experienced engineer to drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems, covering micro-architecture, RTL, verification, performance exploration, and design delivery.

Responsibilities

  • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
  • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
  • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
  • Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
  • Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power

Qualifications

  • Minimum BS and 10+ years of relevant industry experience
  • Experience with microprocessor architecture
  • Experience with logic design principles with timing and power implications
  • Experience in Verilog or VHDL
  • Experience with simulators and waveform debugging process
  • Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction
  • Understanding of low power microarchitecture techniques
  • Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
  • Experience in C or C++ programming
  • Experience using an interpretive language such as Perl or Python

Skills

Required:MicroarchitectureRTL designVerificationPerformance analysis
Nice to have:Coherence protocols / interconnectsMemory subsystem designC/C++ programmingPython/Perl scripting

Benefits

  • Comprehensive medical and dental coverage
  • retirement benefits
  • range of discounted products and free services
  • reimbursement for certain educational expenses including tuition
  • discretionary bonuses or commission payments as well as relocation (eligibility varies)
  • discretionary employee stock programs including stock purchase plan
Last updated Aug 21, 2026. Interested? Apply on the company site.

About Apple

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