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CPU Power Management Microarchitect/RTL Engineer

Apple· Hardware
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Hybrid (Beaverton, Oregon), Hybrid (Santa Clara, California), Hybrid (Waltham, Massachusetts)Full-timePosted 6mo ago

About the role

Apple Silicon Engineering Group seeks an experienced CPU RTL Architect to drive architecture and RTL for world-class CPU power management solutions, contributing from early architectural exploration through detailed specifications, RTL development, verification support, performance exploration, and design delivery.

Responsibilities

  • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
  • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
  • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
  • Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
  • Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power

Qualifications

  • Minimum BS and 10+ years of relevant industry experience
  • Experience with microprocessor architecture
  • Experience with logic design principles with timing and power implications
  • Experience in Verilog or VHDL
  • Experience with simulators and waveform debugging process
  • Expertise in one or more of the following areas: dynamic voltage and frequency scaling (DVFS/DVFM), advanced thermal and energy management, power state definition and management, dynamic clocking solutions, Di/dt mitigation strategies, micro-architecture strategies for improved power integrity, debug solutions, error handling, reset control, clock generation and asynchronous clock crossing strategies
  • Understanding of low power microarchitecture techniques
  • Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
  • Experience in C or C++ programming
  • Experience using an interpretive language such as Perl or Python

Skills

Required:Micro-architectureRTL designVerilog or VHDLSimulation and waveform debuggingPower management techniques
Nice to have:C/C++Python/Perl
Last updated Jun 26, 2026. Interested? Apply on the company site.

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