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RTL Design Engineer

Apple· Hardware
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Hybrid (Austin)Full-timePosted 6mo ago

About the role

Results-oriented RTL Design Engineer sought to join Apple’s mixed-signal silicon design team. The role focuses on specifying, designing, verifying, and bringing up digital and mixed-signal circuits with signal processing capabilities, leveraging Verilog/SystemVerilog, DSP concepts, and collaboration across hardware and software domains.

Responsibilities

  • RTL Design & Implementation: Develop and optimize RTL code in Verilog/SystemVerilog for mixed-signal digital blocks and signal processing pipelines
  • DSP Algorithm Translation: Translate DSP concepts into efficient RTL implementations in collaboration with algorithm engineers
  • Design Verification: Write assertions and unit-level testbenches; participate in functional verification using standard methodologies
  • Integration & Bring-up: Integrate complex IPs with cross-functional teams; validate performance in silicon; support lab characterization
  • Collaborative Problem-Solving: Work with analog designers, algorithm engineers, verification specialists, and system architects across disciplines
  • Specify and/or micro-architect digital and signal processing blocks in sophisticated mixed-signal circuits
  • RTL coding of blocks, including implementation of DSP algorithms
  • Participate in lab bring-up of circuits; write test scripts; analyze lab data; propose experiments; validate signal processing performance

Qualifications

  • BS and a minimum of 10 years relevant industry experience
  • Front-end tools expertise (Verilog simulators, linters, clock-domain crossing checkers)
  • Synthesis, static timing analysis, and design-for-test (DFT)
  • SystemVerilog assertions, checkers, and advanced verification techniques
  • Scripting languages (Perl, Python)
  • Formal verification and low-power design methodologies
  • Hardware-software co-design and system-level optimization
  • Hands-on DSP experience: signal processing concepts, RTL algorithm implementation, hardware optimization techniques (pipelining, parallelization, resource sharing)
  • Intermediate to advanced GenAI proficiency: Using AI tools for SystemVerilog design, validation, optimization, and understanding GenAI capabilities/limitations in hardware design

Skills

Required:Verilog/SystemVerilogDSP conceptsDesign verificationScripting (Perl, Python)
Last updated Jul 3, 2026. Interested? Apply on the company site.

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