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RTL Design Engineer

Apple· Hardware
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Hybrid (Beaverton, OR)full-timePosted 6mo ago

About the role

Beaverton, Oregon-based role in Apple’s mixed-signal silicon design team. Responsible for specifying, designing, verifying, and bringing up digital and mixed-signal circuits with signal processing capabilities, translating DSP concepts into RTL, and collaborating across analog, verification, and architecture teams.

Responsibilities

  • RTL Design & Implementation: Develop and optimize RTL code in Verilog/SystemVerilog for mixed-signal digital blocks and signal processing pipelines
  • DSP Algorithm Translation: Collaborate with algorithm engineers to translate DSP concepts (filtering, transforms, modulation, signal analysis) into efficient, high-performance RTL implementations
  • Design Verification: Write comprehensive assertions, unit-level testbenches, and participate in functional verification using industry-standard methodologies
  • Integration & Bring-up: Partner with cross-functional teams to integrate complex IPs, validate performance in silicon, and support lab characterization
  • Collaborative Problem-Solving: Work effectively with analog designers, algorithm engineers, verification specialists, and system architects across disciplinary boundaries
  • BS and a minimum of 10 years relevant industry experience
  • Front-end tools expertise (Verilog simulators, linters, clock-domain crossing checkers)
  • Synthesis, static timing analysis, and design-for-test (DFT)
  • SystemVerilog assertions, checkers, and advanced verification techniques
  • Scripting languages (Perl, Python)
  • Formal verification and low-power design methodologies
  • Hardware-software co-design and system-level optimization
  • Hands-on DSP experience: signal processing concepts, RTL algorithm implementation, hardware optimization techniques (pipelining, parallelization, resource sharing)
  • Intermediate to advanced GenAI proficiency: Using AI tools for SystemVerilog design, validation, optimization, and understanding GenAI capabilities/limitations in hardware design

Qualifications

  • BS and a minimum of 10 years relevant industry experience
  • Front-end tools expertise (Verilog simulators, linters, clock-domain crossing checkers)
  • Synthesis, static timing analysis, and design-for-test (DFT)
  • SystemVerilog assertions, checkers, and advanced verification techniques
  • Scripting languages (Perl, Python)
  • Formal verification and low-power design methodologies
  • Hardware-software co-design and system-level optimization
  • Hands-on DSP experience: signal processing concepts, RTL algorithm implementation, hardware optimization techniques (pipelining, parallelization, resource sharing)
  • Intermediate to advanced GenAI proficiency: Using AI tools for SystemVerilog design, validation, optimization, and understanding GenAI capabilities/limitations in hardware design

Skills

Required:RTL codingDSP algorithm translationDesign verificationIntegration & bring-up
Nice to have:ScriptingGenAI for hardware design

Benefits

  • Apple unified benefits package (as applicable)
  • EEO and accessibility programs mentioned in description
Last updated Jul 3, 2026. Interested? Apply on the company site.

About Apple

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