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Design Verification Lead

Apple· Hardware
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Hybrid (Austin)Full-timePosted 6mo ago

About the role

Senior Engineering Leader in Silicon Design Verification responsible for leading verification teams, defining verification methodologies, and ensuring first-pass success of silicon designs through scalable, reusable strategies and cross-functional collaboration.

Responsibilities

  • lead, grow and mentor a team of verification engineers, providing technical guidance, career development, and performance management
  • Collaborate with architecture, design, and software teams to define verification requirements, drive verification strategy, planning, environment implementation and methodology
  • define and execute functional and power-aware verification plans, focusing on test coverage, formal verification, and assertion-based verification using SystemVerilog and UVM methodologies
  • provide technical leadership by mentoring, reviewing team members' work, and fostering a culture of innovation and collaboration
  • continuously refine verification strategies to improve efficiency, speed, and completeness
  • drive best practices and ensure first-pass success of silicon designs
  • work with cross functional teams to implement scalable, reusable verification strategies
  • grow and guide a team of talented verification engineers ensuring highest quality silicon products meeting performance, power, and area targets

Qualifications

  • BS and a minimum of 20 years relevant industry experience
  • 12+ years of experience in ASIC/SoC verification, including at least 3 years in a senior leadership role managing teams of engineers
  • Experience with post-silicon validation and debug
  • Familiarity with performance modeling, emulation, or prototyping
  • Hands-on experience with low-power design verification (UPF methodology, clock gating, power intent validation, etc.)
  • Understanding of mixed-signal interactions and analog modeling for verification
  • Background in high-speed interfaces (e.g., PCIe, USB, DDR), power-aware verification methodologies, formal verification, and constrained-random testbenches
  • Proven track record of delivering high-performance silicon with first-pass success
  • Deep expertise in SystemVerilog, UVM, and modern verification methodologies
  • Strong debugging and problem-solving skills for complex SoC designs
  • Experience leading multi-site teams and cross-functional collaboration with architecture, design, and software groups
  • Experience with coverage-driven verification methodologies and regression-driven verification strategies
  • Excellent communication and leadership skills, with a proven track record of developing high-performing teams and mentoring engineers

Skills

Required:SystemVerilogUVMFunctional verificationPower-aware verificationFormal verification
Nice to have:Constrained-random testbenches
Last updated Jul 3, 2026. Interested? Apply on the company site.

About Apple

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

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