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Design Verification Engineer

Apple· Hardware
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Melbourne, FL, Cary, NC, Waltham, MAFull-timePosted 6mo ago

About the role

DV engineer responsible for enabling fully functional first silicon for IP designs, including pre-silicon verification, methodology establishment, test-plan development, verification environment creation, stimulus, checkers, test-writing, debug, coverage, and sign-off for RTL freeze and tape-out.

Responsibilities

  • Study design specification and create test plan
  • Develop infrastructure in SystemVerilog/UVM to stress the design
  • Develop and fix failures from regressions, close bugs
  • Use LLMs to do verification efficiently

Qualifications

  • BS degree in technical subject area and a minimum 10 years relevant industry experience.
  • Deep knowledge of OOP, SystemVerilog and UVM
  • Deep knowledge in developing scalable and portable test-benches
  • Strong experience with verification methodologies and tools such as simulators, waveform viewers, Build and run automation, coverage collection, gate level simulations
  • Working experience using LLMs for efficiency and quality
  • Experience with power-aware (UPF) or similar verification methodology
  • Excellent knowledge of one of the scripting languages such as Python, Perl, TCL
  • Experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
  • Knowledge of formal verification methodology is a plus but not required
  • Knowledge of emulation for verification technologies is a plus but not required

Skills

Required:SystemVerilogUVMOOPtest-benchesverification methodologiesPythonLLMs in verification
Nice to have:PerlTCLPCIeUSBDDRUPF power-aware verification
Last updated Oct 2, 2026. Interested? Apply on the company site.

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