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RFIC Layout Engineer

Apple· Hardware
Apply on company site
Hybrid (Irvine, CA), Hybrid (San Diego, CA), Hybrid (Sunnyvale, CA)$43.07/hr - $76.64/hrfull-timePosted 6mo ago

About the role

RFIC layout engineer role within Apple’s wireless SOC organization, focusing on detailed transistor-level RF/analog layout and top-level integration to deliver energy-efficient wireless silicon and hardware advancements.

Responsibilities

  • Block level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking.
  • Co-work with designers on block-level and top-level floorplanning.
  • Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
  • Top-level layout integration and verification, schedule management.
  • Detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.

Qualifications

  • 8+ year minimum related experience required
  • Good understanding of RC delay, electromigration, and coupling
  • Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems
  • Excellent communication skills and ability to work with multi-functional teams
  • Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing
  • Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS (16nm and lower with FinFet experience)
  • Solid understanding of RC delay, electromigration, and coupling
  • Understanding of guard rings, DNW, PN junctions, and sophisticated process effects such as LOD, WPE, etc.
  • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology
  • Extensive knowledge of CADENCE layout tools
  • Scripting skills in PERL or SKILL are a plus
  • Capability to lead other layout engineers for top-level integration

Skills

Required:RF/analog layoutFinFET CMOS knowledgeCALIBRE DRC/ERC/LVSCadence layout toolsLayout leadershipRC delay, electromigration, couplingDevice matching and parasitics minimizationCommunication and collaboration
Nice to have:Scripting (PERL or SKILL)

Benefits

  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Discounted products and free services
  • Educational expense reimbursement (tuition)
  • Discretionary bonuses or commission payments and relocation eligibility
Last updated Aug 28, 2026. Interested? Apply on the company site.

About Apple

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