STA engineer
Hybrid (Haifa)Posted 6mo ago
About the role
Engineer role on the STA team collaborating with multiple integration groups to develop and validate signoff flows, timing convergence, and block/chip level signoff.
Responsibilities
- Develop/support automated block and full chip level signoff flows
- Full Chip Timing/Noise convergence and full signoff for high quality TO
- Enable hierarchical Timing flows
- Power optimizations
- Generate block level budget and context for correlation with Full Chip
- Drive custom IP integration and custom timing checks flows
- Close work with Design, DFT, architecture and Power team
Qualifications
- 4+ years experience in Static Timing analysis
- Extensive experience with one of the commercial STA tools
- Familiarity with hierarchical design approach, top-down design, timing and physical convergence
- Experience with backend STA closure and Signoff
- Deep understanding of designs' constraints development
- Good understanding of AC timing from specs to implementation
- Good understanding of DFT modes and their constraints
- Good communication skills and team player
- Quick learning of flows and methods
Skills
Required:Static Timing AnalysisSTA toolsHierarchical designBackend STA closureAC timingDFT constraintsCommunicationLearning ability
Last updated Jul 3, 2026. Interested? Apply on the company site.
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