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IP Design Verification Engineer

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Hybrid (Jerusalem)Posted 6mo ago

About the role

Design Verification Engineer role focused on pre-silicon verification to ensure bug-free first silicon IP designs. Responsibilities include DV methodology, test-plan development, environment development with stimulus and checkers, test-writing, debug, coverage, and sign-off for RTL freeze and tape-out. Role spans multiple Apple sites in Israel (Herzliya, Haifa, Jerusalem).

Responsibilities

  • Develop detailed test and coverage plans based on the micro-architecture
  • Develop verification methodology suitable for the IP, ensuring a scalable and portable environment
  • Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage and more.
  • Establish DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
  • Ensure bug-free first silicon for part of the IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture

Qualifications

  • 7+ years’ experience in digital logic design verification
  • Basic knowledge of SystemVerilog and UVM
  • Experience developing UVM based IP test-benches
  • Experience with verification tools such as simulators, waveform viewers, build/run automation, coverage collection and analysis, gate level simulations
  • Strong communication skills and ability to interface with multiple groups
  • Ability to work well in a team and meet tight schedules
  • Excellent knowledge of one of the scripting languages: Python, Perl, TCL (preferred)
  • Experience with serial/parallel protocols such as PCIe or DRAM (preferred)
  • Proven knowledge of formal verification methodology (preferred)
  • In lieu of UVM knowledge, C/C++ experienced level knowledge (preferred)
  • Experience with Lab hands-on debug (preferred)
  • BS.C or MS.C in Electrical Engineering (preferred)

Skills

Required:SystemVerilogUVMVerification tools
Nice to have:Scripting languagesFormal verificationC/C++Lab debugging
Last updated Jul 3, 2026. Interested? Apply on the company site.

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