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Design Verification Engineer

Apple· Hardware
Apply on company site
AustinFull-timePosted 6mo ago

About the role

Design Verification Engineers at Apple verify the functionality and performance of Apple’s premier SOCs, collaborating across design, architecture, and software to ensure SOC/IP/subsystem quality. The role focuses on developing verification methodologies, test plans, and testbenches to meet functional and performance goals across multiple IP subsystems.

Responsibilities

  • Review design and architecture specifications and work closely with design & micro-architecture teams
  • Develop test plans, tests & coverage plans
  • Define verification methodology and testbenches for next generation products
  • Actively communicate and collaborate with design, architecture and software to understand use cases and corner conditions and drive test cases
  • Work on one or several IP types within the SOC (e.g., Neural Engine hardware, DRAM subsystem/memory controller logic, encode/decode systems for codecs, hardware security, High-Speed IO such as PCIe/DisplayPort/MIPI, power management and fabric infrastructure, memory cache management, display subsystem)
  • Own ensuring the quality of the SOC or an IP or subsystem
  • Focus deeply on one main IP or broaden to a collection of subsystems depending on assignment

Qualifications

  • Minimum of BS + 3 years relevant industry experience
  • Skilled in constrained random verification, functional coverage, code coverage, assertion methodology & philosophy
  • Knowledge of SystemVerilog, digital simulation and debug
  • Knowledge of computer architecture and digital design fundamentals
  • SW programming skills with knowledge of data structures and algorithms
  • Experience with Python, Perl, or similar scripting language
  • Ability to work independently to deliver project goals
  • Knowledge of verification methodologies like UVM
  • Experience with C/C++, assembly is a plus
  • Excellent interpersonal skills and the dream to tackle diverse challenges

Skills

Required:Constrained random verificationFunctional coverageCode coverageAssertion methodologySystemVerilogDigital simulationPython
Nice to have:PerlC/C++
Last updated Jun 26, 2026. Interested? Apply on the company site.

About Apple

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