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Experienced GPU Electrical Analysis Engineer

Apple· Hardware
Apply on company site
Hybrid (Cambridge), Hybrid (London)Full-timePosted 6mo ago

About the role

GPU Electrical Analysis Engineer within Apple’s Silicon Technologies group responsible for electrical analysis closure from early design planning to tapeout, with hands-on experience in physical design and large chip integration, focusing on power delivery, power integrity, and interaction with the Physical Design team to optimize PD, PNR, and overall GPU performance.

Responsibilities

  • Experience planning, implementing, and analyzing power delivery networks.
  • Experience designing and analyzing power delivery schemes with power switches.
  • Experience with Signal/Power Integrity checks including Electromigration, Static IR and Dynamic Voltage drop checks.
  • Experience with global power integrity tool (e.g. Redhawk, Voltus).
  • Minimum of BS/MS in EE + years of relevant experience.
  • Experience with on-die high frequency power delivery, and exposure to off-die concepts and models.
  • Experience with bump planning and Redistribution Layer routing strategies, including methods for IO bumps and edge encroachment scenarios.
  • Familiar with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
  • Background with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative technologies.
  • Track record in solving complex PD and cross functional problems, driving results directly and/or directing a team of engineers to innovate and execute on world class GPU designs.
  • Circuit design and simulation background a plus, but not required.
  • Experience with global timing verification, SPICE simulation/analysis, and Physical Design Verification Flows.

Qualifications

  • Experience planning, implementing, and analyzing power delivery networks.
  • Experience designing and analyzing power delivery schemes with power switches.
  • Experience with Signal/Power Integrity checks including Electromigration, Static IR and Dynamic Voltage drop checks.
  • Experience with global power integrity tool (e.g. Redhawk, Voltus).
  • Minimum of BS/MS in EE + years of relevant experience.
  • Experience with on-die high frequency power delivery, and exposure to off-die concepts and models.
  • Experience with bump planning and Redistribution Layer routing strategies, including methods for IO bumps and edge encroachment scenarios.
  • Familiar with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
  • Background with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative technologies.
  • Track record in solving complex PD and cross functional problems, driving results directly and/or directing a team of engineers to innovate and execute on world class GPU designs.
  • Circuit design and simulation background a plus, but not required.
  • Experience with global timing verification, SPICE simulation/analysis, and Physical Design Verification Flows.

Skills

Required:Power delivery network planningPower delivery scheme design with power switchesSignal/Power Integrity checks (Electromigration, Static IR, Dynamic Voltage Drop)Global power integrity tools (Redhawk, Voltus)On-die high frequency power delivery conceptsBump planning and redistribution layer (RDL) routing strategiesASIC integration including Floorplanning, Clock/Power distribution, I/O planning, hard IPCross-functional PD problem solving and leadershipGlobal timing verification, SPICE, and PD verification flows
Nice to have:Large SoC design experience (>20M gates, >1GHz)Circuit design and simulation (plus, not required)
Last updated Jul 3, 2026. Interested? Apply on the company site.

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