SoC DFX Scan / ATPG Engineer
Hybrid (Markham, Canada), Hybrid (Ottawa, Canada)CA$128k - CA$192kFull-timePosted 6mo ago
About the role
Role focused on SoC Design-for-Test (DFT) with responsibilities spanning scan insertion, ATPG execution, and DFT methodology development for next-generation AMD SoCs. Collaboration across architecture, design, verification, physical design, and product engineering to drive test quality, manufacturability, and silicon bring-up.
Responsibilities
- Drive end-to-end SoC-level scan insertion, DFT implementation, and ATPG execution.
- Develop and optimize scan architectures, scan chains, test compression, and ATPG strategies.
- Analyze scan coverage and ATPG results to improve test quality and coverage.
- Support ATPG retargeting and hierarchical test integration methodologies.
- Debug scan, ATPG, simulation, and emulation issues from block level through full-chip integration.
- Develop and validate methodologies for stuck-at, transition, at-speed, and diagnostic pattern generation.
- Collaborate with design, verification, physical design, CAD, and product engineering teams to resolve DFT-related challenges.
- Support silicon bring-up, manufacturing test development, yield improvement, and failure analysis activities.
- Contribute to DFT planning and implementation of technologies such as scan compression, MBIST, LBIST, PLL-based at-speed testing, and on-chip debug infrastructure.
- Develop automation and scripting solutions to improve DFT productivity, quality, and scalability.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Skills
Required:DFT fundamentalsScan insertionATPGDigital design fundamentals
Nice to have:Test compressionVerilog/SystemVerilogScriptingSoC-level ATPG retargetingEmulation-based DFT validationsilicon bring-upMBIST/LBIST/JTAG
Last updated Oct 15, 2026. Interested? Apply on the company site.
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