← All roles

Pre‑Silicon Power Modeling Leader — x86 SoCs

AMD· Engineering
Apply on company site
Hybrid (Austin, TX)$178.4kFull-timePosted 6mo ago

About the role

Lead SoC-level pre-silicon power modeling to deliver Perf/Watt projections, DVFS/AVFS plans, and silicon correlation for AMD's embedded and client x86 programs.

Responsibilities

  • Own the SoC power model end‑to‑end using AMD’s converged methodology, delivering accurate workload‑based power estimates for CPU/GPU/NPU, fabric/interconnect, memory, and I/O.
  • Define use‑case power envelopes across automotive, networking, storage, industrial, and robotics segments; partner with product/marketing to derive representative workloads and KPIs.
  • Drive DVFS/AVFS strategy (P‑states, C‑states, voltage/frequency points), telemetry requirements, and FW hand‑offs based on model outputs; provide early tables and guardrails to FW/BIOS.
  • Establish IP/subsystem power budgets; run sensitivity studies to guide architectural decisions (e.g., cache sizes, fabric frequencies, NPU/GPU configurations).
  • Build repeatable model‑to‑silicon correlation plans (CaC/static/dynamic splits, EDC/TDC interactions, droop mitigation) and maintain a power scorecard for program reviews.
  • Lead tool flows & automation (e.g., PowerArtist, PrimeTime PX; Python‑based pipelines) to ingest activity (FSDB/VCD), generate reports, and publish dashboards for stakeholders.
  • Collaborate across Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP to ensure converged Perf/Watt outcomes from concept through bring‑up.

Qualifications

  • Demonstrated experience building top‑level SoC power models with high correlation to silicon, including IP‑level VBM integration and workload‑based projections.
  • Hands‑on with EDA/tooling: PowerArtist, PrimeTime PX (or equivalents), activity annotation (FSDB/VCD), UPF/CPF power intent, Python for automation.
  • Deep knowledge of x86 micro‑architecture (CPU pipelines, caches), GPU/NPU basics, memory subsystems, interconnect/fabric behavior, and power delivery/PDN interactions.
  • Proven ability to define DVFS/AVFS strategies and drive FW telemetry requirements; familiarity with EDC/TDC/CaC semantics and their impact on power.
  • A validated SoC power model & scorecard that anchors program power budgets and executive reviews.
  • Workload‑specific DVFS/AVFS tables and telemetry specs for FW/BIOS enablement.
  • Correlation reports (estimated vs. measured) and recommendations that accelerate first‑time‑right silicon.

Skills

Required:SoC power modelingEDA/tooling (PowerArtist, PrimeTime PX)Python automationx86 micro-architectureDVFS/AVFS strategyPower telemetry & FW integrationCorrelations (CaC/EDC/TDC)
Nice to have:Data visualization (Dashboards)

Benefits

  • Benefits offered are described: AMD benefits at a glance.
Last updated Oct 15, 2026. Interested? Apply on the company site.
AMD logo

About AMD

together we advance_AI

AMD delivers leadership high-performance and adaptive computing solutions to advance data center AI, AI PCs, intelligent edge devices, gaming, & beyond.

AIData CenterHigh-Performance ComputingGamingEdge Devices
Company profileWebsite

More open roles at AMD