Sr. Fellow -- Memory PHY Architect
Hybrid (Bay Area, CA / Boston, MA / Austin, TX / Toronto, Canada)$289.6k - $434.4kFull-timePosted 6mo ago
About the role
Senior technical leader role shaping the future of memory interface technology and Memory PHY solutions at AMD, with architectural direction across DDR, LPDDR, GDDR, and HBM in advanced CMOS technologies. Focus on long-term impact, technical ownership, and cross-functional collaboration without primary people management responsibilities.
Responsibilities
- Serve as a senior technical authority and architect for Memory PHY technology, shaping long-range roadmaps and architectural direction.
- Define and evolve architectures and specifications for advanced Memory PHYs, including DDR, LPDDR, GDDR, and HBM.
- Drive innovation in high-speed I/O circuit design, system-level analysis, power integrity, and signal integrity.
- Partner with cross-functional teams across Circuit Design, Layout, Logic Design, Physical Design, Firmware, Design Verification, and Post-Silicon organizations worldwide.
- Influence design quality and execution through design reviews, technical mentorship, and principled tradeoff decisions.
- Support post-silicon bring-up, validation, characterization, optimization, and product readiness.
- Communicate complex technical concepts clearly to senior technical peers, leadership, and stakeholders.
- Mentor and advise engineers and architects, contributing to a strong and inclusive technical community.
Qualifications
- Advanced degree in Electrical Engineering or related field preferred, or equivalent professional experience.
- Typically, 15+ years of experience in high-speed analog, mixed-signal, or memory PHY design.
Skills
Required:Memory PHY architectureHigh-speed analog and mixed-signal designCMOS technology knowledgeCross-functional collaboration
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 15, 2026. Interested? Apply on the company site.
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