← All roles

Design Verification Engineer

Apple· Hardware
Apply on company site
San Diego, CA, Austin, TX, Sunnyvale, CA$122.7k - $214.3kfull-timePosted 6mo ago

About the role

Design Verification Engineer at Apple focusing on verification of high-throughput cellular baseband modems and RF link controllers for Apple’s SOCs. Responsibilities include building reusable UVM environments, coverage-driven and directed test cases, and driving verification methodology innovation to ensure tape-out readiness and high-quality cellular IP and subsystems.

Responsibilities

  • Construct detailed test plans for various components of the design including use cases, through collaborative work with multi-functional teams.
  • Create coverage driven verification plans from specifications, review and refine to achieve coverage targets.
  • Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and reference models.
  • Leverage Large Language Models (LLMs) to enhance verification processes, delivering improvements in efficiency and quality.
  • Design and implement ML-driven workflows that increase team productivity and overall quality of verification.
  • Implement test plans from RTL simulation bring-up to sign-off; report and debug failures.
  • Maintain regressions and report the verification progress against test plans and coverage metrics.

Qualifications

  • Minimum requirement of a bachelor's degree.
  • Knowledge of System Verilog and UVM.
  • Experience with System C, C/C++, Python/perl.
  • Ability to develop and establishing DV Methodologies.
  • Ability to use LLMs and MCPs.
  • Ability to develop Python-based automation solutions.
  • Understanding of constraint random testing, SVA, Coverage driven verification.
  • Test planning and problem-solving skills.
  • Master of Science degree in Electrical Engineering/Computer Science.
  • Experience in C/C++ modeling for design verification.
  • Knowledge of 4G/5G cellular physical layer operation (3GPP).
  • Experience with verification of embedded processor cores.
  • Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
  • Knowledge of using LLMs to improve efficiency and quality of verification.
  • Understanding of prompt engineering and LLM workflow optimization.

Skills

Required:Test planningUVMSystemVerilogC/C++Python
Nice to have:ML/LLM in verification

Benefits

  • Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs.
  • Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.
  • You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition.
  • discretionary bonuses or commission payments as well as relocation (may be eligible).
  • Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html
Last updated Jul 3, 2026. Interested? Apply on the company site.

About Apple

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

AirPods Max 2Apple ArcadeApple CardApple Fitness+Apple MusicApple TVApple TV+Apple Watch Series 11
Company profileWebsite

More open roles at Apple