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Design Verification Engineer

Apple· Hardware
Apply on company site
Hybrid (San Diego, CA; Austin, TX; Sunnyvale, CA)$175k - $308.5kfull-timePosted 6mo ago

About the role

Design Verification Engineer at Apple focusing on verification of high-throughput cellular baseband modems and RF link controllers within Apple’s SOCs. Develops reusable UVM environments, coverage-driven test plans, and ML-assisted verification workflows to ensure tape-out readiness and high-quality cellular systems.

Responsibilities

  • Construct detailed test plans for various components of the design including use cases, through collaborative work with multi-functional teams.
  • Create coverage driven verification plans from specifications, review and refine to achieve coverage targets.
  • Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and reference models.
  • Leverage Large Language Models (LLMs) to enhance verification processes, delivering improvements in efficiency and quality.
  • Design and implement ML-driven workflows that increase team productivity and overall quality of verification.
  • Implement test plans from RTL simulation bring-up to sign-off; report and debug failures.
  • Maintain regressions and report the verification progress against test plans and coverage metrics.

Qualifications

  • BS and a minimum of 10 years relevant industry experience.
  • Strong knowledge of System Verilog and UVM.
  • Skilled in System C, C/C++, Python/perl.
  • Highly proficient in developing and establishing DV Methodologies.
  • Experience in using LLMs and MCPs.
  • Experience with developing Python-based automation solutions.
  • Experience with constraint random testing, SVA, Coverage driven verification.
  • Strong test planning and problem-solving skills.
  • Master of Science degree in Electrical Engineering/Computer Science.
  • Experience in C/C++ modeling for design verification.
  • Knowledge of 4G/5G cellular physical layer operation (3GPP).
  • Experience with verification of embedded processor cores.
  • Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
  • Experience using LLMs to improve efficiency and quality of verification.
  • Understanding of prompt engineering and LLM workflow optimization.

Skills

Required:Test planningSystemVerilogUVMPythonC/C++DV methodologies
Nice to have:LLMs in verification

Benefits

  • Comprehensive medical and dental coverage
  • retirement benefits
  • a range of discounted products and free services
  • reimbursement for certain educational expenses — including tuition
  • potential discretionary bonuses or commission payments
  • relocation assistance
  • employee stock programs (discretionary RSU, Employee Stock Purchase Plan)
Last updated Jul 3, 2026. Interested? Apply on the company site.

About Apple

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

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