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CPU Physical Electrical Analysis Engineer

Apple· Hardware
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Hybrid (Beaverton, OR / Santa Clara, CA)Full-timePosted 6mo ago

About the role

Engineer driving block and top level design of power-grid and analysis of high performance compute blocks in the EMIR/SIGEM/Reliability space, with cross-functional collaboration across CAD/EDA vendors, methodology teams, implementation teams, and SoC level teams to ensure design and sign-off closure.

Responsibilities

  • Drive block and top-level EMIR/electrical verification closure
  • Work on power grid design, construction, and implementation using existing infrastructures and where necessary, creating custom solutions in PNR tool environment
  • Work multi-functionally with CAD/EDA vendors to ensure fidelity of analysis results; with methodology teams to cover unique use cases; with implementation teams to drive design and sign-off closure, and with the SoC level teams to meet IP delivery quality and schedule

Qualifications

  • Minimum BS and 10+ years of relevant industry experience
  • Experience with PNR design implementation and STA
  • Knowledge of computer architecture and RISC pipelines with experience working on compute-oriented block implementation (GPU / Neural network / CPU PNR blocks)
  • Experience in TCL-based automation with PNR & STA tools
  • Familiarity with industry standard tools such as Siemens, Ansys Redhawk, Seascape, or Cadence Voltus
  • Working knowledge of C/C++
  • Ability to write and maintain scripts in TCL, Python, or Perl
  • Experience with data analysis techniques using Python or Perl
  • Experience with matplotlib / pandas or similar data analytics packages

Skills

Required:EMIR/electrical verificationPower grid designPNR/STA toolingTCL/Python/Perl scriptingC/C++

Benefits

  • Equal opportunity employer benefits (as per Apple policies)
Last updated Aug 28, 2026. Interested? Apply on the company site.

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