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Graphics (GPU) Design Verification Engineer

Apple· Hardware
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Austin, TXFull-timePosted 6mo ago

About the role

Role within Apple’s Silicon Engineering group, part of the GPU Shader Core team, focusing on verification of power-efficient, high-performance graphics processor microarchitectures for mobile devices and PCs. Lead verification efforts for Unified Shader Core units/sub-systems, architect test benches, and drive verification strategy and delivery.

Responsibilities

  • Lead verification teams for one or more units or sub-systems within the Unified Shader Core
  • Own the overall development, execution and tracking of the team’s infrastructure and test plans
  • Architect test bench infrastructure using System Verilog / Universal Verification Methodology
  • Define overall verifications strategies, including stimulus, checking, coverage and regressions
  • Assist in the development, maintenance, debug and closure of test bench infrastructure
  • Drive discussions with GPU µArch, Design and other multi-functional teams to coordinate verification efforts and meet overall program goals
  • Generate and present weekly status to GPU leadership

Qualifications

  • BS + 10 years of relevant Design Verification experience
  • Background in CPU or GPU architectures, or equivalently complex IPs
  • Experience in architecting test benches with System Verilog and UVM or OVM
  • Experience with constrained randoms verification and functional coverage analysis
  • Experience in debugging highly complex logic designs and Object Oriented software
  • Experience with HDL simulators and waveform viewers (IES, VCS, DVE, Verdi, etc.)
  • Expertise in GPU or SIMD architectures
  • Experience in leading a verification team from project concept through final closure
  • Experience in driving the completion of specifications, sign-off checklists, and reviews
  • Experience with scripting languages such as Python, Ruby, or Perl
  • Excellent communication skills and ability to collaborate effectively with multiple teams
  • Ability to manage multiple priorities under strict schedule deadlines

Skills

Required:SystemVerilogUVM/OVMConstrained random verificationFunctional coverage analysisHDL simulators and waveform viewersPython/Ruby/PerlGPU/SIMD architecturesDebugging complex logic designsTest bench infrastructureCommunication and collaboration
Last updated Jul 3, 2026. Interested? Apply on the company site.

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