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CPU Physical Design Engineer

Apple· Hardware
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Hybrid (Beaverton, OR)full-timePosted 6mo ago

About the role

Apple Silicon Engineering Group (SEG) is hiring CPU block-level physical design engineers to drive RTL-to-GDS design convergence, deliver block-level physical design with backend flow closure, and collaborate across CAD, methodology, memory macros, and top-level CPU features.

Responsibilities

  • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA goals
  • Be responsible for block-level physical design delivery along with closure of backend flows, electrical requirements and improving silicon yield
  • Work closely with internal CAD and PD methodology teams on industry-standard synthesis/PNR tool features and optimizations and their adoption in CPU design
  • Collaborate with x-functional top-level teams on CPU floorplan, timing, power, reliability, and testability
  • Work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA

Qualifications

  • Minimum BS and 10+ years of relevant industry experience
  • Experience in logic design and digital circuits
  • Experience with Perl or TCL
  • Experience in low power, high frequency physical design techniques leveraging advanced syn/PnR tool features, and best in class physical design methodology
  • Experience using industry standard logic Synthesis, PnR, STA and Power analysis tools, along with timing budgeting, floor-planning, physical integration, and verification to converge complex designs
  • Knowledge in deep sub-micron technology, along with its implications to timing, power, and area
  • Excellent communication and interpersonal skills
  • Ability to work independently and/or lead a physical design partition in collaboration with x-functional teams

Skills

Required:Logic designPerl or TCL

Benefits

  • (Not listed in the provided description)
Last updated Jul 10, 2026. Interested? Apply on the company site.

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