← All roles

CPU Implementation Engineer

Apple· Hardware
Apply on company site
Hybrid (Beaverton, OR), Hybrid (Santa Clara, CA)Full-timePosted 6mo ago

About the role

CPU block-level implementation engineer role within Apple’s Silicon Engineering Group (SEG), focusing on micro-architecture collaboration, RTL-to-GDS design convergence, backend flow closure, and cross-functional collaboration to deliver high-performance CPU designs.

Responsibilities

  • Work with micro-architects to help define the micro-architecture and assist with design feasibility and power, performance, and area (PPA) trade-offs
  • Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for PPA
  • Responsible for block-level design delivery along with closure of backend flows, electrical requirements, and improving silicon yield
  • Work closely with internal CAD and PD methodology teams on industry-standard synthesis/PNR tool features and optimizations and their adoption in CPU design
  • Work with cross-functional top-level teams on CPU floorplan, timing, power, reliability, and testability
  • Collaborate with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA

Qualifications

  • Minimum BS and 10+ years of relevant industry experience
  • Experience in logic design and digital circuits
  • Experience with low power and high frequency design techniques
  • Experience with TCL or Perl
  • Familiarity with high performance CPU microprocessor architecture and memory sub-system
  • Knowledge in deep sub-micron technology along with its implications to timing, power, and area
  • Proficiency in using industry standard logic Synthesis, PnR, STA and Power analysis tools along with floor-planning, physical design partitioning, and timing budgeting, to converge complex designs
  • Excellent communication and interpersonal skills
  • Ability to work independently and/or lead a physical design partition in collaboration with x-functional teams

Skills

Required:Micro-architecture collaborationRTL-to-GDS design convergenceBackend flow closureSynthesis/PNR/STA toolsFloorplanning and physical design partitioningTCL or Perl
Last updated Jul 24, 2026. Interested? Apply on the company site.

About Apple

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

AirPods Max 2Apple ArcadeApple CardApple Fitness+Apple MusicApple TVApple TV+Apple Watch Series 11
Company profileWebsite

More open roles at Apple