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SoC DFT Engineer

Apple· Hardware
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Hybrid (Austin, TX), Hybrid (Cupertino, CA)full-timePosted 6mo ago

About the role

DFT engineer responsible for developing and implementing DFT architecture and infrastructure for SoC design, collaborating with DV, test, and design teams to verify implementations, generate test vectors, improve coverage, and support silicon bring-up.

Responsibilities

  • Developing and implementing DFT architecture
  • Implementing DFT infrastructure
  • Working with the DV team to verify DFT implementations and implement ECOs
  • Generating structural test vectors and analyzing and improving coverage
  • Working with designers on STA, physical, power and logical issues
  • Working with test engineers to bring up test vectors on silicon
  • Running schedules and supporting multi-functional engineering efforts

Qualifications

  • BS with a minimum of 0 years relevant industry experience
  • Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
  • Experience developing DFT specifications and driving DFT architecture and methods for designs
  • Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools
  • Knowledge of industry standards for DFT and design tools
  • Proven understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon
  • Experience in debugging Compressed ATPG patterns, MBIST, and JTAG/1500 related issues
  • Experience with STA constraints development and analysis for DFT modes and SDF simulations
  • Ability to conduct experiments during silicon debug, gathering and analyzing data; and use scripting to support efficient handling of ATE data

Skills

Required:DFT architectureDFT infrastructureVerilog/VHDLATPG, JTAG, MBISTDV methodologiesSTA/SDFScriptingDebugging silicon issues
Last updated Jul 17, 2026. Interested? Apply on the company site.

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