← All roles

ASIC Design STA Engineer

AMD· Engineering
Apply on company site
Hybrid (San Jose, CA)$166.4k - $249.6kFull-timePosted 6mo ago

About the role

AMD is seeking an ASIC Design STA engineer to contribute to the development of large SoCs with multiple clock domains, focusing on building and verifying timing constraints, SDC development, and TCL scripting across front-end RTL and back-end synthesis/route flows.

Responsibilities

  • Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
  • Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency
  • Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks
  • collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows
  • Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts)

Qualifications

  • Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field

Skills

Required:Timing constraints development (multi-mode / multi-corner)RTL quality metrics and automationPre-route timing checks and QoR cleanupScripting (Tcl)
Nice to have:EDA tools (Design Compiler, Primetime, Spyglass, Fishtail etc.)
Last updated Oct 15, 2026. Interested? Apply on the company site.
AMD logo

About AMD

together we advance_AI

AMD delivers leadership high-performance and adaptive computing solutions to advance data center AI, AI PCs, intelligent edge devices, gaming, & beyond.

AIData CenterHigh-Performance ComputingGamingEdge Devices
Company profileWebsite

More open roles at AMD