Lead IP Block level Verification Engineer
HyderabadFull-timePosted 6mo ago
About the role
Verification role at AMD leading and contributing to the verification of Network on Chip (NOC) IPs, subsystems and SOC designs, using simulation and formal methods to prove functional correctness.
Responsibilities
- Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
- Interact with architects and design engineers to create a comprehensive verification testplan
- Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
- Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
- Debug tests with design engineers to deliver functionally correct design blocks
- Identify and write coverage measures for stimulus quality improvements
- Perform coverage analysis to identify verification holes and achieve closure on coverage metrics
Qualifications
- Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+Yrs of exp
- Experience with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES
- Strong understanding of verification techniques including assertion and coverage-driven verification
- Strong understanding of ASIC/full custom chip development phases
- Experience with block level NOC verification is a plus
- Verification experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus
- Experience as a verification architect or establishing verification methodology/tools/infrastructure for high performance FPGAs/SOCs/VLSI designs is a plus
- Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus
- Familiarity with verification management tools and regression management is a plus
- Experience with formal property checking tools such as Cadence IEV, Jasper and Synopsys VC-Formal/Magellan is a plus
Skills
Required:SystemVerilogUVMVerilog
Nice to have:SystemVerilog Assertions (SVA)
Benefits
- AMD benefits at a glance
Last updated Oct 15, 2026. Interested? Apply on the company site.
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