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CPU Design Timing Engineer

Apple· Hardware
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Hybrid (Austin, TX)full-timePosted 6mo ago

About the role

Role focused on timing closure for a high-performance CPU project, collaborating with RTL/implementation teams and the CAD team to develop timing flows, run timing analysis, and drive timing closure across multiple clock and power domains.

Responsibilities

  • Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency
  • Working extensively with CPU micro-architects and implementation engineers to drive timing closure for the CPU

Qualifications

  • Minimum BS and 3+ years of relevant industry experience
  • Experience with script writing and debugging in TCL, Perl, Python
  • Implementation experience on high performance CPU designs
  • Working knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs
  • Good understanding of physical design tools and methodology including physically aware synthesis and place & route tools and flows, extraction, and other analysis flows, and physical design verification (LEC, DVS, etc.)
  • Experience working on timing for 1 ghz+ designs, including how to handle multiple clock and power domains
  • Experience with one of the following static timing tools: Primetime or Tempus
  • Experience with cross talk, noise, OCV, uncertainty, and derate methodology

Skills

Required:Scripting (TCL, Perl, Python)CPU timing closurePhysical design tools and flowsStatic timing analysis toolsCross talk, noise, OCV, uncertainty, derate methodology

Benefits

  • EEO and accessibility commitments described in the posting
Last updated Aug 28, 2026. Interested? Apply on the company site.

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