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DDR Design Engineer

Apple· Hardware
Apply on company site
Beaverton, OregonFull-timePosted 6mo ago

About the role

DDR PHY design role in Beaverton, OR focusing on RTL design, verification, and silicon bring-up for high-performance, low-power DDR PHY designs within Apple’s DDR PHY design team.

Responsibilities

  • Perform concept studies and provide direction on performance, gate count, and power for digital designs
  • Write detailed design specifications and test plans in collaboration with architecture, circuit designers and verification engineers
  • Provide high-quality RTL description, including assertions, for the design
  • Use formal tools and static checkers to guarantee RTL quality
  • Support design verification to ensure bug-free first silicon
  • Drive functional and code coverage as well as timing closure for designs
  • Support silicon bring-up, performance and power characterization
  • Contribute to timing closure and ensure successful silicon bring-up and characterization

Qualifications

  • Bachelor of Science in Electrical Engineering
  • RTL design using Verilog or SystemVerilog, assertion writing
  • Design of state machines, data paths, arbitration and clock domain crossing logic
  • Logic synthesis, timing constraints
  • Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
  • Unified Power Format for simulation, synthesis and electrical rule checking
  • Equivalence checking
  • Prior experience in DDR PHY design and mixed-signal environment is a plus

Skills

Required:RTL designDesign of state machines and data pathsLogic synthesis and timing constraints
Nice to have:Design For Test (DFT) and scanPower/Performance/Area optimization (UPF/UPF)
Last updated Jul 3, 2026. Interested? Apply on the company site.

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