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DDR Design Engineer

Apple· Hardware
Apply on company site
Cupertino, CA$129.3k - $225.3kFull-timePosted 6mo ago

About the role

DDR PHY design team role focusing on RTL design, verification, timing closure, and silicon bring-up for high-performance, low-power applications in Apple’s DDR PHY design group.

Responsibilities

  • Perform concept studies and provide direction on performance, gate count, and power for digital designs.
  • Write detailed design specifications and test plans in collaboration with architecture, circuit designers, and verification engineers.
  • Provide high-quality RTL description, including assertions, for the design.
  • Use formal tools and static checkers to guarantee RTL quality.
  • Support design verification to ensure bug-free first silicon.
  • Drive functional and code coverage as well as timing closure for designs and support silicon bring-up, performance and power characterization.

Qualifications

  • Bachelor of Science in Electrical Engineering.
  • RTL design using Verilog or SystemVerilog, assertion writing.
  • Design of state machines, data paths, arbitration and clock domain crossing logic.
  • Logic synthesis, timing constraints.
  • Exposure to Design For Test, understanding of scan concept and writing DFT-friendly RTL.
  • Unified Power Format for simulation, synthesis and electrical rule checking. Equivalence checking.
  • Prior experience in DDR PHY design and mixed-signal environment is a plus.

Skills

Required:RTL designAssertionsState machines and data pathsLogic synthesisUnified Power Format (UPF)Equivalence checking
Nice to have:Design For Test (DFT)

Benefits

  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Discounted products and free services
  • Educational expense reimbursement including tuition
  • Discretionary bonuses or commissions and relocation (eligibility may vary)
Last updated Jul 3, 2026. Interested? Apply on the company site.

About Apple

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