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PLL Design Engineer

Apple· Hardware
Apply on company site
Austin, TXFull-timePosted 6mo ago

About the role

Role in Apple’s Analog-Mixed/Signal group focused on developing high-quality IPs and cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies. Emphasis on ownership, collaboration, and impact within a fast-paced environment.

Responsibilities

  • Develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies
  • Contribute to maintaining Apple’s leadership in innovation and market presence
  • Work on PLL/FLL and frequency synthesis architecture and circuit design (digital and analog approaches, DCO/VCO design RO and LC, Fractional-N, SSC, Spur and Jitter cancellation techniques)
  • Understand band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques
  • Model and simulate systems, develop SystemVerilog models, perform behavioral simulations to explore architectural performance and loop dynamics
  • Possibly design/debug RTL
  • Collaborate with team, apply strong problem-solving and detail-oriented approaches
  • Demonstrate innovation, leadership, and a growth mindset

Qualifications

  • BSEE with 0 years of relevant experience
  • Proficiency in PLL/FLL and frequency synthesis architecture and circuit design (digital and analog approaches)
  • Experience or understanding of DCO/VCO design (RO and LC), Fractional-N, SSC, Spur and Jitter cancellation techniques
  • Solid understanding of clocking fundamentals, phase noise, jitter analysis, budgeting, and feedback loop dynamics
  • Experience in SystemVerilog modeling and behavioral simulations; RTL design/debug is a plus
  • Attention to detail and ability to assess systemic impacts
  • History of innovation and self-directed learning; demonstrated leadership and growth mindset
  • Strong teamwork, productivity, and scripting skills; experience with industry-standard design tools

Skills

Required:PLL/FLL designDCO/VCO designFractional-N, SSC, Spur/Jitter cancellationClocking and phase noise analysisSystemVerilog modeling
Nice to have:RTL design/debug

Benefits

  • Equal opportunity employer with commitment to inclusion and diversity
  • Accessibility and accommodation programs for applicants
  • Content notes on workplace accessibility and reasonable accommodations
Last updated Oct 23, 2026. Interested? Apply on the company site.

About Apple

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