SR ASIC Design Engineer - NoC & AXI Interconnect
Santa Clara, CA$200k - $300kFull-timePosted 5mo ago
About the role
ASIC design role focused on high-performance network chips (AINIC and DPU) with front-end design/integration responsibilities, collaborating across architecture, IP design, Physical Design, and product engineering to achieve first-pass silicon success.
Responsibilities
- Network-on-Chip (NoC) design and integration
- AXI, ACE, and APB interface design and verification
- Queuing system design and implementation
- Collaboration with architecture, IP, and physical design teams for first-pass silicon success
- Post-silicon bring-up support and yield learning
Qualifications
- Bachelors or Masters degree in computer engineering or Electrical Engineering
Skills
Required:NoC architecture and designAXI, ACE, and APB interface design and verificationVerilog/SystemVerilog RTLScripting
Nice to have:Queuing system design and buffer management
Last updated Oct 22, 2026. Interested? Apply on the company site.
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