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Design Verification Engineer

AMD· Engineering
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Santa Clara, CA$166.4kFull-timePosted 4mo ago

About the role

Design Verification Engineer for AMD's Network Technologies Solutions Group (NTSG), focusing on verification architecture, testbench development, and cross-functional collaboration to deliver high-performance ASIC designs for data center networking and AI/data center workloads.

Responsibilities

  • Develop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.

Qualifications

  • Bachelor’s Degree in Electrical/Computer Engineering or related field, Master’s Preferred
  • Expert-level knowledge of SystemVerilog and UVM
  • Strong hands-on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)
  • Proven experience in verifying complex IP/subsystems with test plans, coverage, and constrained-random methodologies
  • Strong debug skills across architecture, RTL, and testbench layers
  • Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data-path components
  • Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure

Skills

Required:SystemVerilogUVMSystemVerilog simulatorsWaveform debuggingDebugging RTL/TestbenchNetworking protocolsPython/Scripting

Benefits

  • AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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