Staff DFx Methodology Architect
San Jose, CA$166.4k - $249.6kFull-timePosted 4mo ago
About the role
DFx Architecture, Methodology and Logic Design Expert to support FPGA-SoCs and custom ASICs, owning DFx architecture definition, RTL implementation and methodology development within AMD’s AECG organization.
Responsibilities
- Define and lead SoC-DFx Architecture, Specifications and development of DFx-IPs
- Own DFx Architecture documentation, accounting for interactions with other features, the hardware and the firmware
- Implement DFx features in RTL using Verilog/SystemVerilog
- Co-owning Timing and Design Quality Checks (and waivers) for the DFx-IPs
- Work cross functionally with DFx execution and verification teams to enable integration and validation of DFx-IPs in all phases of design implementation flow
- Work closely with Design teams for Verification Test plan reviews, Timing targets and Performance/Power Verification sign offs
- Engage with validation and product teams on test plan, coverage, Silicon bring up and silicon debug
- Contribute to front-end, DFx and timing methodologies
- Drive innovation in a rapidly changing technological environment
Qualifications
- Bachelors or Masters or PhD degree in Computer / Electrical Engineering
Skills
Required:DFx ArchitectureRTL DesignTiming
Nice to have:DFT/DFx ToolsScripting
Last updated Oct 22, 2026. Interested? Apply on the company site.
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