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CPU Design Timing Engineer

Apple· Hardware
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Beaverton, ORFull-timePosted 4mo ago

About the role

CPU block-level timing engineer responsible for timing closure and developing timing flows in Apple’s Silicon Engineering Group for high-performance CPU designs.

Responsibilities

  • Working with the CAD team to develop the timing flow used on the project, including scripting to improve analysis flows and engineer efficiency
  • Working extensively with CPU micro-architects and implementation engineers to drive timing closure for the CPU

Qualifications

  • Minimum BS and 10+ years of relevant industry experience
  • Experience working on timing for 1 GHz+ designs, including handling multiple clock and power domains
  • Experience with one of the following static timing tools: Primetime or Tempus
  • Experience with cross talk, noise, OCV, uncertainty, and derate methodology
  • Experience with script writing and debugging in TCL, Perl, or Python
  • Implementation experience on high performance CPU designs
  • Working knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs
  • Good understanding of physical design tools and methodology including physically aware synthesis, place & route, extraction, and physical design verification (LEC, DVS, etc.)
  • Knowledge of static timing tools and flows including handling multiple clock and power domains
  • Knowledge of device physics especially aspects which impact timing: cross talk, noise, OCV, uncertainty and derate methodology

Skills

Required:Timing analysisStatic timing analysis toolsScripting
Last updated Jul 3, 2026. Interested? Apply on the company site.

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