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Senior ASIC Design Verification Engineer

K2 Space· Silicon
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Remote$170k - $250kFull-timePosted 4mo ago

About the role

Senior-level ASIC design verification role focused on verifying functionality, performance, and robustness of custom silicon. Involves defining verification approach, developing methodologies, and collaborating across architecture, RTL, DFT, firmware, physical design, and silicon validation to shape first-generation silicon in a fast-growing, remote-enabled space-tech company.

Responsibilities

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Participate in ASIC team interviews.
  • Contribute to advancement of DV methodologies and improvements.
  • Engage external IP providers and verification partners when needed.

Qualifications

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
  • Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
  • Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
  • Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).

Skills

Required:SystemVerilogUVMConstrained-random testing
Nice to have:Formal verification

Benefits

  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
Last updated Aug 26, 2026. Interested? Apply on the company site.

About K2 Space

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Building the largest satellites in orbit. Ultra-powerful, scalable platforms engineered for LEO–cislunar missions. Explore the next-generation of satellites.

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