Senior SoC Power Modeling Engineer
Hybrid (Austin, TX)$178.4k - $267.6kFull-timePosted 4mo ago
About the role
Senior Power Modeling Engineer focusing on pre-silicon power modeling and analysis for Embedded x86 SoC platforms, translating workloads into SoC-level power models and guiding early architecture trade-offs.
Responsibilities
- Develop and maintain SoC-level power models for Embedded x86 platforms using IP-level inputs (CPU, GPU, fabric, memory, and I/O).
- Create use-case-driven power models representing automotive, industrial, edge computing, and customer-specific embedded workloads.
- Translate real-world workloads into model inputs such as activity factors, concurrency, residency, and DVFS states.
- Build and maintain Voltage‑Frequency (VF) curves across operating corners.
- Derive and validate EDC / TDC / current limits based on modeled workloads and platform constraints.
- Perform sensitivity studies across frequency, voltage, workload mix, and power states.
- Integrate IP‑level power models into cohesive SoC‑level frameworks.
- Ensure consistency of assumptions across IPs (clocking, power states, gating, DVFS).
- Identify gaps, inconsistencies, or inaccuracies in IP models and drive closure with IP teams.
- Partner with SoC and power architects to influence early architectural decisions.
- Evaluate power/performance/area trade‑offs for new features, configurations, and SKUs.
- Support bounding‑box analysis and product positioning decisions.
- Support pre‑silicon to post‑silicon correlation of power models.
- Refine models using silicon data, profiling, and validation feedback.
- Improve modeling methodologies, accuracy targets, and documentation.
Qualifications
- Professional experience in power modeling, power estimation, or SoC power analysis
- Strong understanding of SoC power architecture and DVFS
- Static vs dynamic power components
- EDC / TDC / electrical and thermal constraints
- Hands‑on experience building SoC‑level power models from IP‑level models
- Experience creating and analyzing VF curves
- Experience with Embedded or Automotive SoCs
- Familiarity with x86 CPU, GPU, memory, and fabric power behaviors
- Exposure to power modeling tools, spreadsheets, or internal frameworks used for pre‑silicon estimation
- Experience with workload‑driven modeling and benchmark abstraction
- Strong analytical and scripting skills (Python preferred)
- Ability to work across architecture, IP, performance, and validation teams
- Prior involvement in power correlation with silicon
- Ability to clearly communicate modeling assumptions and results to senior technical stakeholders
Skills
Required:SoC power modelingVF curvesIP‑to‑SoC model integrationDVFS
Nice to have:Pre/post‑silicon correlationPython
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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