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Principal Cache RTL Design - CPU Team

AMD· Engineering
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Hybrid (Bangalore)Full-timePosted 4mo ago

About the role

Principal Cache RTL Design role within AMD's CPU team focusing on RTL design, power management, cache coherency, and inter-IP integration for high-performance x86-core features. Hybrid work location in Bangalore, India; senior-level position requiring extensive digital IP/ASIC experience and leadership responsibilities.

Responsibilities

  • RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
  • Architect and design of power management features, cache, coherency.
  • Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
  • Responsible for the inter IP integration issues resolution
  • Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem.
  • Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design
  • Architecting, micro-architecting and documentation of the design features
  • Lead design team from all aspects of the RTL deliverables.
  • Mentor the junior members of the RTL team to meet the team goals
  • Represents AMD to the outside technical community, partners and vendors
  • Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.

Qualifications

  • 15+ years of experience in Digital IP/ASIC design and Verilog RTL development
  • Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification.
  • Should be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation.
  • Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects.
  • Should possess expertise in front-end EDA tools sign-off and its flows.
  • Familiarity with low power design and low power flow is an added plus.
  • Ability to program with scripting languages such as Python or Perl is a plus;
  • Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements;
  • Proven interpersonal skills, leadership and teamwork;
  • Excellent writing skills in the English language, editing and organizational skills required;
  • Skilled at prioritization and multi-tasking;
  • Good understanding of engineering terminology used within the semiconductor industry;
  • Good understanding of digital design concepts;
  • Knowledge of, or experience in, functional design verification or design is highly desired.

Skills

Required:RTL designPower management designCache coherency designClock-Domain CrossingLeadership / mentorship

Benefits

  • Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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