Firmware Memory Engineer
Hybrid (Austin, TX), Hybrid (Boxborough, MA)$178.4kFull-timePosted 4mo ago
About the role
The Memory IO team is seeking firmware designers to work on pre/post-silicon development of high-speed memory interfaces (LPDDR, DDR, inter-chip IO IPs) and to contribute across microarchitecture, firmware/hardware co-design, and bring-up of Memory PHYs and interface IP in collaboration with RTL, FW, circuit and architecture teams.
Responsibilities
- Firmware design and development of DDR PHY & DRAM Training steps
- Firmware development of DDR PHY for ATE Testing, IP Char & SoC Power
- Pre-silicon FW coding and simulation against Architectural and RTL models
- Post-silicon lab bring-up and optimization of DDR Init and Run Time FW
- Post-silicon DDR Training enhancements to enable robust links for higher reliability / higher frequency margin
- Working with SoC/Product firmware teams to define features and specs
Qualifications
- Bachelor's degree in Electrical or Computer Engineering (strongly desired)
- Master's or PhD degree a plus
- Excellent knowledge of C, C++ and scripting language (e.g., Python)
- Good knowledge of Verilog/SystemVerilog and digital simulation debugging
- Ability to adapt to new toolsets and frameworks
- Strong understanding of synchronization techniques; knowledge of hardware level clocking and synchronization is a plus
- Post-silicon experience developing firmware on real hardware is required; experience with SERDES, DDR, Memory Controller Design preferred
- Strong understanding of computer organization/architecture
- Laboratory experience with oscilloscopes, logic analyzers, etc.
- Experience with low level, physics-oriented logic design (IO, clocking, voltage control) is an asset
Skills
Required:CC++Verilog/SystemVerilogDigital simulation debuggingPre/post-silicon FW development
Nice to have:PythonDDR PHY / SERDESLaboratory hardware skills
Benefits
- AMD benefits at a glance (link provided)
Last updated Oct 15, 2026. Interested? Apply on the company site.
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