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Custom Timing and Verification CAD Engineer

Apple· Hardware
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Hybrid (Austin, TX), Hybrid (Sunnyvale, CA)Full-timePosted 4mo ago

About the role

Entry-level CAD engineer responsible for developing and maintaining flows for transistor-level timing verification (NanoTime) and formal verification (ESP), supporting design teams, driving verification closure, and contributing to methodology documentation and tool improvements across programs and technology nodes.

Responsibilities

  • Develop, maintain, and improve CAD flows and automation scripts for NanoTime and ESP
  • Support design teams in setting up timing and verification runs, interpreting results, and resolving tool and methodology issues
  • Drive timing and formal verification closure in collaboration with circuit designers
  • Contribute to methodology documentation and guidelines adopted across programs and design organizations
  • Engage with EDA vendors to report issues, evaluate new features, and drive tool improvements
  • Build automation to improve flow efficiency, reduce runtime, and scale support across concurrent programs

Qualifications

  • Minimum of BS degree in Electrical Engineering, Computer Engineering, Computer Science, or related field + 10 years relevant industry experience
  • Strong programming or scripting experience in Perl, Python, TCL, or similar language
  • Solid understanding of digital or custom IC design at transistor level and static timing analysis
  • Hands-on experience with transistor-level timing and formal verification tools such as NanoTime, ESP, PrimeTime, or HSPICE, including flow ownership and methodology development
  • In-depth knowledge of dynamic logic, memory arrays, or mixed-signal circuit techniques, and ability to debug complex timing and verification issues independently
  • Experience with SPICE netlists, device models, and parasitic extraction formats such as DSPF or SPF in the context of timing sign-off
  • Experience with formal verification methodologies and SystemVerilog RTL, including RTL-to-schematic equivalence checking
  • Track record of driving cross-functional collaboration with design, layout, and EDA vendor teams to resolve tool and methodology issues
  • Experience developing or contributing to organization-wide CAD methodology documentation and best practices
  • Familiarity with AI/ML-driven CAD workflows and interest in applying GenAI techniques to flow automation and timing analysis
  • Strong communicator with the ability to present technical work clearly to both peers and management, and drive issues to resolution across teams

Skills

Required:Programming/scriptingTransistor-level timing verificationFormal verificationTool ownership and methodology developmentCross-functional collaborationDocumentation

Benefits

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
  • (Note: Benefits are not explicitly itemized beyond this EEO statement; if there were explicit benefits in the posting they would be listed here)
Last updated Aug 7, 2026. Interested? Apply on the company site.

About Apple

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