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Principal ASIC Physical Design Engineer

K2 Space· Silicon
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Seattle, WA$190k - $280kFull-timePosted 3mo ago

About the role

Lead the implementation of complex SoCs for next-generation satellite and space systems, owning the full physical design flow from RTL handoff to GDSII, coordinating with architecture, RTL, DFT, packaging, and external partners to ensure first-pass silicon success in advanced FinFET technologies.

Responsibilities

  • Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
  • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
  • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
  • Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
  • Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
  • Support chip bring-up and debug through close collaboration with post-silicon and test teams.
  • Support your product through production and spaceflight.

Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
  • Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Skills

Required:RTL-to-GDSII flowPPA optimizationMulti-Voltage/Multi-Clock designFinFET tech nodesDFT/STA

Benefits

  • Base salary range for this role is $190,000 – $280,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
Last updated Aug 26, 2026. Interested? Apply on the company site.

About K2 Space

Build Bigger

Building the largest satellites in orbit. Ultra-powerful, scalable platforms engineered for LEO–cislunar missions. Explore the next-generation of satellites.

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