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RTL Design Engineer

AMD· Engineering
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Markham, ONCA$128kFull-timePosted 3mo ago

About the role

RTL Design Engineer in AMD's Security IP (SECIP) team focused on block level RTL design and MP subsystem integration for SoC products across AMD business units, including client, servers, graphics, and gaming. Roles involve design, verification, leadership, and collaboration to advance security, performance, and power management within embedded micro-processor subsystems.

Responsibilities

  • Develop and maintain block level RTL IP and MP subsystems’ feature spec, micro-architecture, synthesizable RTL design methodology and infrastructure
  • Develop and debug RTL designs using C-DPI directed test methodology, and/or using verification team’s testbenches and tests, and achieve design feature closure (feature spec vs. coverage metrics)
  • Triage regressions, debug specific simulations, analyze coverage, and work/resolve technical issues with design, verification, and other teams to achieve design feature and design rule closures (linting, timing, DFT, DFP and other rules)
  • Participate in verification testbench and test plan specification, influence testbench architecture development (design for verification aspect), review and improve feature and coverage test plans
  • Debug and resolve integration issues with SoC Integration, SoC DV and post-silicon validation teams
  • Provide technical leadership in IP functionality and design methodology development as well as critical problem resolution if as advanced level team members

Qualifications

  • Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field
  • Master's Degree preferred

Skills

Required:VerilogScriptingC-DPIAXI/AMBA/Bus protocolsASIC design tools
Nice to have:System VerilogLeadership

Benefits

  • Benefits offered are described: AMD benefits at a glance
Last updated Oct 15, 2026. Interested? Apply on the company site.
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