← All roles

Senior ASIC Physical Design Engineer

K2 Space· Silicon
Apply on company site
Hybrid (United States)$170k - $250kfull-timePosted 3mo ago

About the role

Senior ASIC Physical Design Engineer to implement advanced SoCs for satellite and space systems, contributing to the full physical design flow from synthesis to GDSII, achieving timing closure and PPA optimization, and supporting design integration with external partners in a fast-paced, space-focused environment.

Responsibilities

  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
  • Develop and maintain scripts and automation to improve flow efficiency and consistency.
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
  • Assist in chip-level integration, ECOs, and tapeout preparation.
  • Contribute to methodology development, tool evaluation, and flow documentation.
  • Support your product through production and spaceflight.

Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
  • 5–10 years of experience in ASIC physical design for complex SoCs.
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
  • Strong understanding of timing analysis, power optimization, and physical verification flows.
  • Experience with hierarchical or flat SoC design methodologies.
  • Familiarity with FinFET technologies.
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Skills

Required:ASIC physical designSynthesisFloorplanningPlace & RouteTiming analysisPower optimizationDFT/UPF/CPF
Nice to have:Chip-package co-design

Benefits

  • Base salary range for this role is $170,000 – $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks
Last updated Aug 26, 2026. Interested? Apply on the company site.

About K2 Space

Build Bigger

Building the largest satellites in orbit. Ultra-powerful, scalable platforms engineered for LEO–cislunar missions. Explore the next-generation of satellites.

SatellitesSpacecraftLEOMEOGEOSatellite Power
Company profileWebsite

More open roles at K2 Space