Sr. Design Verification Engineer
Santa Clara, CA$200kFull-timePosted 3mo ago
About the role
Senior CPU Design Verification Engineer responsible for building scalable CPU testbench infrastructure and verification environments for next-generation server processors, collaborating with global teams, applying modern methodologies including AI-driven techniques.
Responsibilities
- Develop and maintain CPU-level testbench infrastructure using C++
- Build scalable verification environments supporting CPU subsystems and core-level validation
- Write and enhance tests and components using C++, SystemVerilog, and UVM
- Collaborate with design, verification, and debug teams across global locations
- Debug testbench and design issues using software models and analysis tools
- Contribute to verification quality metrics and coverage closure
- Support integration of testbench infrastructure with broader verification workflows
- Apply modern methodologies, including AI-driven techniques, to improve verification efficiency
Qualifications
- Strong C/C++ programming and software development skills
- Experience building or maintaining verification testbenches
- Understanding of CPU or processor microarchitecture
- Background in design verification (CPU, memory, networking, or similar domains)
- Experience with SystemVerilog and UVM
- Familiarity with RTL design (Verilog or equivalent)
- Scripting experience (Python, Perl, or similar)
- Bachelors or Masters degree in Electrical Engineering preferred
Skills
Required:C++SystemVerilogUVM
Nice to have:RTL designPython
Last updated Oct 15, 2026. Interested? Apply on the company site.
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