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ASIC Design Engineer — Neural Engine DMA

Apple· Hardware
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Sunnyvale$184.7k - $324.8kFull-timePosted 3mo ago

About the role

ASIC Design Engineer responsible for designing high-performance DMA engines moving model weights and activation tensors between memory and Apple Neural Engine (ANE) memory subsystem. End-to-end ownership from microarchitecture specification through tapeout, collaboration across design, verification, architecture, and physical implementation teams, and mentoring junior engineers.

Responsibilities

  • Taking end-to-end ownership of DMA subsystems through the full cycle: microarchitecture specification, RTL implementation, front-end signoff (synthesis, timing closure, area and power analysis, linting, LEC), and design verification closure.
  • Writing well-parameterized RTL structured for clean timing and low power, including assertions and cover points that encode design intent and ensure verification completeness.
  • Collaborating across design, architecture, and physical implementation teams to make sound architectural trade-offs and drive solutions that meet performance, power, and area targets.
  • Working closely with design verification and formal verification teams to ensure functional correctness: reviewing test plans, debugging failures, and confirming the design's intended behavior is fully exercised.

Qualifications

  • Bachelors Degree plus 10 years of industry experience
  • Experience designing SoC front-end RTL in Verilog or SystemVerilog through multiple tapeouts, including synthesis, timing closure, area and power analysis, linting, and logic equivalence checks.
  • Experience collaborating across design verification, formal verification, architecture, and physical implementation teams to specify, implement, and debug complex RTL blocks.
  • Experience designing DMA microarchitecture: address sequencing, flow control, arbitration, or transaction ordering.
  • Experience with on-chip bus protocols (AMBA AXI, AHB, APB) and on-chip interconnect fabrics.
  • Background in adjacent high-bandwidth domains: networking SoCs, image and video processing pipelines, multimedia IP, or AI/ML accelerators.
  • A track record of writing precise, thorough micro-architectural specifications that serve as the authoritative reference for design, verification, and integration teams.
  • Familiarity with scripting languages (Python, Perl, Tcl) for design automation.

Skills

Required:RTL design (Verilog/SystemVerilog)DMA architectureOn-chip bus protocols (AXI, AHB, APB)Collaboration across teams (verification, architecture, physical implementation)Verification (design, formal)

Benefits

  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Discounted products and free services
  • Educational expense reimbursement for career advancement
  • Discretionary bonuses or commissions possible
  • Relocation assistance possible
  • Apple employee stock programs and Employee Stock Purchase Plan
Last updated Aug 7, 2026. Interested? Apply on the company site.

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