RTL Design Engineer
HyderabadFull-timePosted 3mo ago
About the role
RTL Design Engineer with 4-5 years of SOC integration and RTL design experience, focusing on subsystem IP for AMD/AECG SoCs, including protocols (AXI, UFS, SDIO, Octal SPI), micro-architecture understanding, and cross-functional collaboration.
Responsibilities
- Develop IO peripheral Subsystem for Processor (ARM, RISC-V) subsystems for AMD/AECG SoCs.
- Experience in one of the protocol and integration of UFS, SDIO, Octal SPI needed
- Drive end-to-end Subsystem IP and SoC design collateral from concept to production.
- Collaborate with cross-functional team members
- Ensure timely delivery of projects while meeting quality standards.
- Provide strong technical solution to internal and external stakeholders.
Qualifications
- Proven experience in SOC design roles with focus on RTL design of subsystem IP for about 4-5 years
- Expertise in Micro-architecture design and presentation
- Expertise and strong understanding of RTL quality checks and constraints for Subsystem IP
- Excellent communication skill
- Strong analytical and problem-solving abilities, including designing experiments for performance
- Self-motivated and proactive in driving initiatives.
- Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering.
Skills
Required:RTL designMicro-architectureSubsystem IP constraints and quality checksCommunicationAnalytical / problem-solving
Nice to have:UFS / SDIO / Octal SPI
Benefits
- Benefits offered are described: AMD benefits at a glance (link provided in job description)
Last updated Oct 22, 2026. Interested? Apply on the company site.
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