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Design Verification Engineer

AMD· Engineering
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Santa Clara, CA$166.4k - $249.6kFull-timePosted 3mo ago

About the role

Design Verification Engineer responsible for verification of DDR interfaces and memory systems (DDR5, LPDDR5/LPDDR6, DFI) for server products, leveraging SystemVerilog, UVM, C/C++, and scripting languages; located in Santa Clara, CA.

Responsibilities

  • Work with a team verification engineers in the development and execution of verification plan for DDR5, LPDDR5, and DFI memory systems in server products.
  • Comprehend the PHY's interaction in the complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface.
  • Understand RTL and micro-architecture sufficiently to engage in cross functional discussions with IP/Domain architects and Design engineers for planning and debug.
  • Knowledge sharing and other contributions to verification methodology
  • Support Post-Si teams for Product Performance, Power and functional issues debug/resolution

Qualifications

  • Bachelor’s or Master’s degree in related discipline preferred
  • Excellent communication, management, and presentation skills.

Skills

Required:SystemVerilogUVM (Universal Verification Methodology)C/C++DDR5/LPDDR5/DFI knowledge
Nice to have:Python/Perl
Last updated Oct 22, 2026. Interested? Apply on the company site.
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